The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, it relates to a technology effectively applicable to a semiconductor device having MISFETs, and manufacturing thereof.
Over a semiconductor substrate, a gate insulation film is formed. Over the gate insulation film, a gate electrode is formed. Thus, by ion implantation or the like, source/drain regions are formed. As a result, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) can be formed. For such a MISFET, there is known the following technology: to the interface between the gate insulation film and the gate electrode, namely, to the top of the gate insulation film, a trace amount of metal such as hafnium (Hf) is added, thereby to reduce the impurity concentration of the channel region; as a result, the threshold voltage (Vth) is adjusted.
Japanese Unexamined Patent Publication No. 2006-093670 (Patent Document 1) describes the following technology: a metal such as hafnium (Hf) is caused to be present at the interface between the gate electrode and the gate insulation film; as a result, the threshold voltage (Vth) is adjusted.
Japanese Unexamined Patent Publication No. 2006-332179 (Patent Document 2) describes the following technology: a metal such as hafnium (Hf) is introduced into the vicinity of the interface between the gate electrode and the gate insulation film; as a result, the impurity concentration of the channel necessary for achieving the same threshold voltage (Vth) is adjusted so as to be reduced.
WO08/035598 (Patent Document 3) describes the following technology: the gate insulation film is set to be a HfSiON film, and the work function of the gate electrode is adjusted; as a result, the threshold voltage (Vth) is adjusted.
Whereas, there is known the following technology: the type of the metal to be added is varied between an n channel type MISFET and a p channel type MISFET forming a complementary type MISFET; as a result, the transistor characteristics such as threshold voltage (Vth) are adjusted.
WO08/015940 (Patent Document 4) describes the following technology: the type of impurities contained in the Ni silicide region between the gate insulation film and the gate electrode is varied between an n channel type MISFET and a p channel type MISFET; as a result, the threshold voltage (Vth) is adjusted.
Japanese Unexamined Patent Publication No. 2010-103386 (Patent Document 5) describes the following technology: a diffusion preventive film containing Al or the like is formed in the gate insulation film in only the p channel type MISFET; as a result, the flat band voltage is adjusted.
Japanese Unexamined Patent Publication No. 2007-288096 (Patent Document 6) describes the following technology: as a first gate insulation film of an n channel type MISFET, and a second gate insulation film of a p channel type MISFET, a high-k film containing hafnium (Hf) is used; and in order to make even the gate leakage currents of both the MISFETs, the film thickness of the first gate insulation film is set larger than the thickness of the second gate insulation film.
Japanese Unexamined Patent Publication No. 2008-288465 (Patent Document 7) describes the following technology: as the gate insulation film of an n channel type MISFET, a high-k film containing hafnium (Hf) is used, and as the gate insulation film of a p channel type MISFET, a silicon oxide film is used.
Japanese Unexamined Patent Publication No. 2011-009321 (Patent Document 8) describes the following technology: over a region in which a p channel type MISFET is formed, for example, a HfO film with a thickness of 1.0 nm is formed, and over a region in which an n channel type MISFET is formed, for example, a HfO film with a thickness of 1.5 nm is formed.
On the other hand, when a metal such as hafnium (Hf) is added to the gate insulation film, a metal is crystallized by heat load, which may result in the reduction of the reliability of the gate insulation film. However, by allowing the gate insulation film to include a silicon oxynitride film (SiON film) functioning as a barrier layer, it is possible to improve the reliability of the gate insulation film even when a metal is added thereto. Namely, it is an effective method for improving the reliability of the gate insulation film to use a silicon oxynitride film (SiON film) functioning as a barrier layer in the gate insulation film containing a metal such as hafnium (Hf).
Japanese Unexamined Patent Publication No. 2003-008011 (Patent Document 9) describes the following technology: there is used a gate insulation film having a high-k film formed of a hafnium oxide film (HfO2 film) containing silicon (Si), and a lower barrier film formed of a silicon oxynitride film (SiON film) containing hafnium (Hf) formed on the bottom side of the high-k film.
Japanese Unexamined Patent Publication No. 2010-161299 (Patent Document 10) describes the following technology: the surface density of hafnium (Hf) in the n channel type MISFET is set smaller than the surface density of hafnium (Hf) in the p channel type MISFET, and the nitrogen concentration of a silicon oxynitride film (SiON film) in the n channel type MISFET is set smaller than the nitrogen concentration of a silicon oxynitride film (SiON film) in the p channel type MISFET.
[Patent Documents]
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2006-093670
[Patent Document 2]
Japanese Unexamined Patent Publication No. 2006-332179
[Patent Document 3]
WO08/035598
[Patent Document 4]
WO08/015940
[Patent Document 5]
Japanese Unexamined Patent Publication No. 2010-103386
[Patent Document 6]
Japanese Unexamined Patent Publication No. 2007-288096
[Patent Document 7]
Japanese Unexamined Patent Publication No. 2008-288465
[Patent Document 8]
Japanese Unexamined Patent Publication No. 2011-009321
[Patent Document 9]
Japanese Unexamined Patent Publication No. 2003-008011
[Patent Document 10]
Japanese Unexamined Patent Publication No. 2010-161299